1. Field of the Invention
The present invention relates to a pulse generator suitable for a digital-to-analog converter (which will be shortly referred to as a "D/A converter"), in which a highly accurate analog signal is obtained by a simple low-pass filter. More specifically, the present invention relates to a D/A converter converting a digital signal into a pulse-width-modulated (i.e., PWM) signal which is then converted into an analog signal, and especially to a PWM pulse generator in such a D/A converter.
2. Description of the Prior Art
U.S. Pat. No. 2,907,021 discloses a D/A converter which receives an input digital signal and generates a pulse with the pulse width varied in accordance with the input signal, which pulse switches a reference voltage to generate a pulse signal with a constant voltage amplitude which is in turn filtered by means of a low-pass filter thereby to obtain a direct current signal (which will be shortly referred to as a "DC signal"). In a PWM pulse generator used in the D/A converter disclosed, the value of a counter made operative for a constant period is compared with an input digital signal and the PMW signal corresponding to the input digital signal is fed out. More specifically, a flip-flop is reset at a timing corresponding to a repetition period, e.g., when the value of the counter becomes 0. The flip-flop is set when the value of the counter and the input digital signal are compared and found to be coincident. By these operations, a signal having a pulse width which is proportional to the digital input signal value is generated. The generated signal is smoothed to obtain a DC voltage which has a value corresponding to the product of the reference voltage the ratio of the pulse width to the repetition period. As is apparent from the conversion principle, the accuracy of the outpuut DC voltage is dependent upon the accuracy of the ratio of the pulse to the repetition period. Therefore, it is made possible to obtain a highly accurate D/A converter by increasing the bit number of the counter. Hence an increase in the bit number is accompanied with a rise of the clock frequency for digital synchronized circuits such as the counter or a drop of the generated pulse frequency (i.e., the elongation of the duration of the repetition period). A rise of a clock frequency and the drop of the generated pulse frequency are both undesirable, because the switching speed of field effect transistors used in large-scale integration circuits is relatively low and therefore the clock frequency cannot be raised without introducing noise, and the drop of the repetition frequency of the generated pulse necessitates the increase in the time constant of a low-pass filter for smoothing the generated pulse so that the size of the low-pass filter will be enlarged.
In order to prevent a drop of the repetition frequency of the generated pulse, therefore, it has been proposed to divisionally generate a PWM signal corresponding to each input digital signal thereby to increase the frequency component of the generated pulse. This method is disclosed in U.S. Pat. No. 3,603,977. This will be described in connection with an example of the D/A conversion of n bits. In the method disclosed in the U.S. Pat. No. 2,907,021, only one PWM signal having a pulse width of a duration corresponding to each input digital signal is generated for a repetition time t corresponding to a value 2.sup.n. In the system disclosed in the U.S. Pat. No. 3,603,977, on the other hand, a pulse of a pulse width .tau. to be generated is divided into a k number of PWM signals and is dispersed for the repetition time t. As a result, the k number of the PWM signals have a repetition time of t/k so that its frequency can be increased k times. The total width of the pulse widths .tau..sub.1, .tau..sub.2, . . . , and .tau..sub.k of the respective small pulses becomes equal to the pulse width of the time .tau. corresponding to the input digital signal in this case. This method, in which one DC voltage is generated by a plurality of divided PWM signals, is superior to the conventional method in which one DC voltage is generated by one PWM signal. However, these divided PWM signals have the following defect. This pulse has its minimum variation width at the width corresponding to one period of a clock frequency. As a result, upon the minimum variation of the pulse width, the width of only one of the k number of pulses is enlarged by one period of the clock frequency. Then, the generated PWM signal still contains the lower frequency component having a period of the time t.
In the D/A converter disclosed in the U.S. Pat. No. 3,603,977, therefore, sufficient attenuation can be attained for the main frequency included in the k number of pulses with the use of a simple low-pass filter which has a smaller time constant and poor cut-off frequency characteristic and which is constructed of a resistor, a capacitor and so on. For the lower frequency having the period of the time t of the pulse component corresponding to the lowest bit conversion, however, the smoothing effect of the simple low-pass filter is not very effective.